Contact:
Megan Moran
Aldec, Inc.
(702) 990-4400 ext. 201
meganm@aldec.com

Henderson Nevada, August 6th, 2001-- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), and Synplicity (NASDAQ: SYNP), a leading supplier of software for the design and verification of semiconductors, have entered into a strategic OEM relationship to offer a highly integrated, advanced FPGA design solution. The product contains Aldec's Active-HDL design and verification tools along with Synplicity's Synplify FPGA logic synthesis software. This integrated solution offers users a complete set of tools from design entry through logic synthesis and interfaces to all IC vendor implementation tools. With this new offering, users will have complete control over the FPGA process with the highest performance tools available.

High-density FPGA designers will benefit the most from the "best-in-class" mixed VHDL, Verilog and EDIF simulation and logic synthesis tools provided in this package, although major benefits can be seen at all levels of FPGA design.

"The product was a simple and natural fit, resulting in the most advanced FPGA design tool suite available. It solves the new design challenges brought by the ultra-dense FPGA devices," stated Megan Moran, Product Marketing Manager for the Active-HDL product line at Aldec.

Integration
Designers will significantly benefit from the tight integration between Active-HDL and the Synplify software. For example, Aldec's Design Flow Manager will allow push button initialization of the Synplify software and all files generated by the logic synthesis software will be back annotated into Active-HDL. The Design Flow Manager is an effective project management tool to control all stages of the design process from design entry through logic simulation and synthesis. All software elements are controlled through the graphical Design Flow Manager, which allows the selection of simulation, synthesis and place and route settings, and viewing reports and cross-probe error messages.

Mixed VHDL, Verilog and EDIF Design
As the amount of design using mixed languages and IP Cores escalates, the demand for flexible tools becomes increasingly more important. The ability to freely mix IP cores with VHDL, Verilog and EDIF during the design process makes the combination of Active-HDL and Synplify software an extremely versatile tool for today's design requirements. The ability to reuse old designs as new blocks for a current design shortens the development process, helping to move products to market faster. The additional benefit of simulating an EDIF netlist instead of a VHDL or Verilog netlist is that it is the same netlist that is being passed to the place and route tools.

Advanced Logic Synthesis
Joe Gianelli, director of business development at Synplicity, said, "We are pleased to be able to continue our relationship with Aldec to offer our mutual customers a complete FPGA design solution from design entry through synthesis. The tight integration between our tools, and the high performance and ease of use offered by our Synplify product will enable FPGA designers to achieve high quality of results in a short time frame."

Availability
Active-HDL with Synplify will be available August 6, 2001 and will be sold exclusively by Aldec. The product is available as either a floating or node-lock license and includes Synplicity's Synplify synthesis, as well as Aldec's HDL Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation. All product sales include one year of maintenance in the purchase. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.

About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.